1. Field of the Invention
The present invention relates generally to memory systems and
2. Description of the Prior Art
Content addressable memories are used to find matches between an input data signal and data stored in a memory. Traditional content addressable memories have comparison circuitry imbedded in each cell of the memory array. This allows the input signal to be compared with all entries within the memory at the same time. This traditional design is very fast, in that a complete catalogue of all matching entries can be made available within approximately one memory cycle of the underlying memory array.
Such an approach is also relatively expensive. Inclusion of comparison circuitry in the memory array requires more cell area than is required in a conventional static random access memory (SRAM) cell. The physical chip size of such a content addressable memory is quite large for higher density devices.
If comparison functions other than a direct comparison, such as less than, greater than or equal to, and so forth, are to be used, the number of transistors used for each cell can easily be doubled over a standard SRAM cell. This more than doubles the layout area of the cell, resulting in a large device.
A large content addressable memory would be useful at a system level for many applications. For example, database searching, and other searching and selection applications, often perform simple comparisons on a large block of data. Presently, these searches are performed using software by scanning through a large number of memory locations looking for a match. As is known in the art, this can be an extremely time consuming process. Content addressable memories are not used to perform such functions in hardware because of their small size and high expense.
It would be desirable to provide a large content addressable memory suitable for use with larger search and compare operations. It would further be desirable if such a memory maintained a small chip size and was relatively inexpensive.
It is therefore an object of the present invention to provide a content addressable memory suitable for implementation in an integrated circuit.
It is a further object of the present invention to provide such a content addressable memory which provides access to a relatively large number of entries at a reasonably fast rate.
It is another object of the present invention to provide such a content addressable memory which is simple in design, relatively inexpensive, and compatible with current technology.
Therefore, according to the present invention, a content addressable memory includes a memory array having a plurality of entries. Control circuitry is provided f or sequentially presenting each entry in the array to a comparator. An input signal is also provided to the comparator. Entries matching the input signal are identified for later use. The input signal can be masked, so that only selected fields of each entry are compared to it. Conventional RAM technology can be used for the memory array. In the alternative, a serial memory array, such as an array formed from a charge coupled device, can be used.